This invention relates to image sensors, and more particularly to on chip testing of image sensors.
Analog to digital converters (ADC) are conventionally used to convert analog signals to digital codes or signals for processing. Dedicated ADC chips can be readily tested in manufacturing by applying a known analog input to the chip and evaluating the digital output. Many current microelectronic circuit chips exist in which the ADC is integrated on a substrate with processors and other circuits. Embedded ADCs may be difficult and time-consuming to test in manufacturing. Testing requires access to the digital output data of the ADC to assess the behavior of the ADC. This may be difficult or impossible, particularly when testing at speed.
The ADC can be tested using static techniques. Digital data is accessed via a serial scan path. However, a 16-bit ADC may require a prohibitive number of scan downloads (from a tester or test time perspective) in order to verify that the ADC is functional for every digital code.
On the analog input side of ADC, ramp inputs have traditionally been a preferred technique to stimulate the ADC to output all of its digital output codes. This requires either special mixed signal automatic test equipment (ATE) or additional components on the tester to the device under test interface board.
For image sensors, the output of the ADC of a pixel array is based on the light condition and integration time. At a given light condition, an increase in integration time results in a linear increase in ADC output. As current sensors are mostly frame based, the integration time may only be changed by the frame rate. Thus, to completely perform an on-chip check an 8-bit ADC, it takes 255/30=8.5 sec at 30 frames per second. This is compared to approximately 0.5 seconds for an off-chip ADC test. A system that allows for on-chip ADC testing at an increased speed may be useful.
The present invention increases the speed for on-chip ADC testing of image sensors by testing multiple chips in parallel. A wafer typically has many individual image sensor chips. A parallel on-chip test procedure is operated, power is applied to a plurality of the image sensor chips and the chips are then tested in parallel. Additional power inputs may be added to the wafer in order to allow power to be supplied to a plurality of the image sensor chips at once. These power lines may be etched directly on the wafer, or a wafer master may be used to overlay the wafer with the power lines for testing purposes. Additionally, test engines may be added to the wafer map to control the overall test procedures.